1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device of a low electric power consumption type.
2. Description of the Prior Art
FIG. 1 is a circuit diagram showing the configuration of a circuit capable of performing under a low electric voltage as a semiconductor integrated circuit device that will be used for explanation of preferred embodiments according to the present invention and following conventional examples. The diagram of this circuit capable of performing under the low voltage shown in FIG. 1 was also disclosed in the patent document of Japanese patent laid open publication number JP-A-7/212218 as a conventional semiconductor integrated circuit device.
The circuit capable of performing under a low electrical voltage as a semiconductor integrated circuit device shown in FIG. 1 comprises multi-threshold complementary metal oxide semiconductors (hereinafter also referred to as MT CMOS).
In FIG. 1, the reference number 1 designates a two-input NAND gate. Each of the reference numbers 2 and 3 denotes a p channel type metal oxide semiconductor field effect transistor (hereinafter referred to as a p MOS FET). Each of the reference numbers 4 and 5 indicates n channel type metal oxide semiconductor field effect transistors (hereinafter referred to as a n channel MOS FET). In the circuit shown in FIG. 1, the absolute value of the threshold voltage of this p MOS FET is set to a low value and the absolute value of the threshold voltage of this n MOS FET is set to a high value. The reference number 6 designates a power source of a predetermined voltage, 7 denotes a ground power source. The reference number 8 indicates a p channel MOS FET connected between the power source 6 and a power source line 12 as a hypothetical power source line. This p channel MOS FET 8 becomes active when a gate terminal of the P channel MOS FET 8 receives a control signal 9. The reference number 10 indicates an n channel MOS FET connected between ground 7 and a ground line 13 that is a hypothetical ground line. This n channel MOS FET 10 becomes active when a gate terminal of the n channel MOS FET 10 receives a control signal 11. In this circuit shown in FIG. 1, it is formed so that the absolute values of the threshold voltages of the p channel MOS FET 8 and the n channel MOS FET 10 are higher than the absolute values of the threshold voltages of the p channel MOS FETs 2 and 3 and the n channel MOS FETs 4 and 5 forming the two-input NAND gate 1, respectively.
FIG. 2 is a conventional layout pattern of a memory cell array in a conventional semiconductor integrated circuit device that was disclosed in the patent document of Japanese patent laid open publication number JP-A-8/18021. In FIG. 2, the reference number 210 indicates an array section in which a plurality of MOS FETs are arranged in an array form. The reference numbers 220, 230, 240, and 250 denote input/output circuit forming sections located in a peripheral section of the array section 210, in which input/output circuits are formed. The reference number 260 designates a region in which MOS FETs, each having a high threshold voltage, are formed in the array section 210. Further, the reference number 270 designates a region in which MOS FETs, each having a low threshold voltage, are formed in the array section 210.
Next, a description will be given of the operation of the conventional circuit capable of performing under a low supply voltage as the conventional semiconductor integrated circuit device shown in FIG. 2.
In recent years, there have been significant advancements of technology in portable devices such as mobile telephone devices and the portable devices are widely used in the world. Accordingly, it must be required to operate those portable devices under a lower power voltage in order to maintain the voltage of a battery as long as possible. To reduce the operational voltage used in the portable devices is an effective method to reduce the power consumption of the portable devices as small as possible. Because the power consumption is obtained by multiple of a voltage value and a current value, it is possible to reduce both the voltage value and the current value by reducing the operational voltage of the devices. In general, this method causes to obtain a greatly effect to reduce the power consumption of the devices. However, a MOS FET forming a semiconductor integrated circuit has a drawback in which the operation speed of the MOS FET becomes low according to reducing of the operational voltage. This characteristic of the MOS FET is based on that its threshold voltage is not reduced in proportion to the reducing of the voltage value of the power source. The reason is that the magnitude of a leak current under an off state (an inactive state) of the MOS FET is increased when the threshold voltage of the MOS FET is decreased, so that the power consumption is also increased.
In order to solve the conventional drawback described above, a following conventional method is used.
In the circuit operable under a low voltage shown in FIG. 1, when the two-input NAND gate 1 operates, the level of the control signal (CSB1) 9 is set to a low level and the control signal (CS1) 11, which is an inverted signal of the control signal (CSB1) 9 in voltage level, is set to a high level. Thereby, both the p channel MOS FET 8 and the n channel MOS FET 10 are ON and the voltage potential of the hypothetical power source line 12 rises up to the voltage level of the power source and the voltage potential of the ground line 13 is fallen to the voltage level of the ground GND 7. As a result, two-input NAND gate 1 operates as a normal NAND gate. In this case, because the threshold voltage of each of the MOS FETs 2 to 5 is set to the low value, it is possible to operate the two-input NAND gate 1 at a high speed when the voltage level of the power source 6 is low.
When the two-input NAND gate 1 is not used, the control signal (CSB1) 9 is set to the high level and the control signal (CS1) 11, that is the inverted signal of the control signal (CSB1) 9 in voltage level, is set to the low level. At this time, both the p channel MOS FET 8 and the n channel MOS FET 10 become OFF, so that the hypothetical power source lines 12 and the hypothetical ground line 13 are electrically disconnected from the power source 6 and the ground 7, respectively.
Because it is so formed that the absolute value of the threshold voltage of each of the p channel MOS FET 8 and the n channel MOS FET 10 is higher than that of each of the MOS FETs 2 to 5, it is possible to suppress the value of the leak current within a lower value.
In general, in a region in which the voltage between the gate and the source of a MOS FET is lower than a threshold voltage of the MOS FET, the magnitude of the leak current flowing through the source and the drain is exponentially increased according to the value of the voltage of the gate. It is therefore possible to greatly reduce the leak current when the MOS FETs 2 to 5 and the MOS FETs 8 and 10 have different threshold voltage values.
Although the above conventional example shows the two-input NAND gate 1 comprising MOS FETs, each having the lower absolute value of the threshold voltage, it is possible to apply the above method to many kinds of semiconductor integrated circuits in size and function such as other logical circuits, memory devices, and the like.
FIG. 2 is the conventional layout of the circuit comprising gate arrays capable of performing under a low voltage as the semiconductor integrated circuit shown in FIG. 1. In FIG. 1, both the p channel MOS FET 8 and the n channel MOS FET 10, each having a higher threshold voltage, are formed in regions 260, and the p channel MOS FETs 2 and 3 and the n channel MOS FETs 4 and 5, each having a lower threshold voltage, are formed in regions 270 that are the regions other than the region 260 in the array section 210. Further, the electric power from the power source 6, the ground voltage from the ground 7, and the control signals 9 and 11 are supplied to the array section 210 through input/output circuit regions 220, 230, 240, and 250.
Because the conventional circuit capable of performing under the low voltage as the semiconductor integrated circuit device has the configuration described above, namely, because both MOS FETs having the high threshold voltage and the low threshold voltage are formed in the array section 210, it is difficult to use the regions 260 (that is used for the MOS FETs having the high threshold voltage) in the array section for the internal circuits such as the two-input NAND gate 1 and wiring transferring signals and voltages of power source. Thereby, it becomes necessary to reduce the wiring efficiency in the array section 210 and the peripheral section thereof. This limitation causes to reduce the density of the layout of the semiconductor integrated circuit device.
In addition, in order to obtain a low power consumption, when the MT CMOS is used in a previously designed circuit (or in a pre-designed circuit) in which the MT CMOS is not used, it is difficult to use the pre-designed circuit without changing this layout pattern by the limitation of the regions 260 in the array section 210 in which the MOS FETs having the high threshold voltage are formed. This conventional layout of the circuit causes a drawback that it must be required to design a new layout pattern again.
Accordingly, an object of the present invention is, with due consideration to the drawbacks of the conventional semiconductor integrated circuit device, to provide a semiconductor integrated circuit device as a circuit capable of performing under a lower voltage by forming MOS FETs having a higher threshold voltage in regions other than the array section, capable of improving a layout efficiency and capable of using pre-designed circuits to be used in an array section without any changing of its circuit design and layout pattern.
In accordance with a preferred embodiment of the present invention, a semiconductor integrated circuit device comprises an array section in which a plurality of low threshold voltage metal oxide semiconductor field effect transistors (MOS FETs) are formed in array form, and input/output circuit forming areas other than the array section in which high threshold voltage MOS FETs having a high threshold voltage are formed. In the semiconductor integrated circuit device described above, the threshold voltage of each of the high threshold voltage MOS FETs is higher than a threshold voltage of each of the plurality of low threshold voltage MOS FETs formed in said array section.
In accordance with another preferred embodiment of the present invention, a semiconductor integrated circuit device comprises an array section in which a plurality of low threshold voltage metal oxide semiconductor field effect transistors (MOS FETS) are formed in array form, and input/output circuit forming areas located at peripheral sections of the array section, each area comprising a first area in which input/output circuits are formed and a second area in which MOS FETs whose absolute vale of a threshold voltage being higher than an absolute value of a threshold voltage value of each of the plurality of low threshold voltage MOS FETs formed in the array section.
In accordance with another preferred embodiment of the present invention, a semiconductor integrated circuit device comprises an array section in which a plurality of metal oxide semiconductor field effect transistors (MOS FETs) are formed in array form, and a plurality of areas, located at peripheral sections of the array section, in which high threshold voltage metal oxide field effect transistors (MOS FETs) and low threshold voltage MOS FETs are formed. In the semiconductor integrated circuit device described above, an absolute value of a threshold voltage of each of the high threshold voltage MOS FETs is higher than an absolute vale of a threshold voltage of each of the plurality of MOS FETs formed in the array section, and an absolute value of a threshold voltage of each of the low threshold voltage MOS FETs is lower than the absolute vale of the threshold voltage of each of the high threshold voltage MOS FETs, and each of the plurality of areas has an input/output circuit forming area having a same configuration.
In the semiconductor integrated circuit device as another preferred embodiment of the present invention, the plurality of high threshold voltage MOS FETs are formed at areas of four corners other than the array section and the input/output circuit forming sections in the semiconductor integrated circuit.
In the semiconductor integrated circuit device as another preferred embodiment of the present invention, the plurality of high threshold voltage MOS FETs are formed at space areas between the array section and the input/output circuit forming sections in the semiconductor integrated circuit.
In the semiconductor integrated circuit device as another preferred embodiment of the present invention, switch circuits for supplying power sources to the array section and electrically cutting the power sources from the array section are formed in the input/output circuit forming areas by using the high threshold voltage MOS FETs, and input/output circuits for inputting signals to the array section and outputting the signals from the array section are formed in the input/output circuit forming areas by using both the high threshold voltage MOS FETs and the low threshold voltage MOS FETS.